I am currently pursuing a Master’s degree in Integrated Circuit Science and Engineering at the School of Integrated Circuits (集成电路学院), Shanghai Jiao Tong University (SJTU), Shanghai, China, under the supervision of Professor Guanghui He. I also work closely with Professor Chen Zhang and Professor Zihan Wu.

My current research interests focus on Efficient ASIC Architecture Design and Efficient Algorithms for Embodied AI.

• Efficient Hardware Accelerators for Embodied AI
  • Robotics diffusion models: sparse accelerator with fine-grained caching (DAC 2026).
  • 3D Gaussian Splatting: hardware acceleration with hierarchical reuse and dynamic partitioning (DAC 2026).
• Efficient Algorithms for Embodied AI
  • Vision-Language-Action Models (VLA): depth-guided grasp refinement without retraining (ICLR 2027, under review).
  • World Action Models (WAM): drift-adaptive speculative inference with parallel verification (AAAI 2027, under review).

🔥 News

• 2026.03:  🎉 Our paper SpRDA about sparse acceleration for robotics diffusion models is accepted by DAC’26. One co-authored paper PipeGS about hardware acceleration for 3D Gaussian Splatting is accepted by DAC’26.

📝 Publications

Selected Publications

DAC 2026

SpRDA: An Efficient Sparse Accelerator for Robotics Diffusion Model

Renda Jian, Yuzhou Chen, Pan Zhao, Yitian Chen, Zhican Wang, Xueling Wang, Chen Zhang and Guanghui He

• Proposed a fine-grained, difference-aware caching method to exploit redundant computation in robotics diffusion models, achieving over 90% sparsity.
• Designed a dynamic sparsity-aware matrix processing array and a graph-based vector unit to accelerate both matrix and non-matrix operators.
• Achieved 1.56–2.60× throughput and 6.45–7.85× energy efficiency compared with state-of-the-art diffusion accelerators.
• 2026 63rd ACM/IEEE Design Automation Conference (DAC)

Full Pub List

• DAC 2026 SpRDA: An Efficient Sparse Accelerator for Robotics Diffusion Model, Renda Jian, Yuzhou Chen, Pan Zhao, Yitian Chen, Zhican Wang, Xueling Wang, Chen Zhang and Guanghui He, in Proceedings of the 63rd ACM/IEEE Design Automation Conference, 2026.
• DAC 2026 PipeGS: Unlocking 3DGS Pipeline Parallelism via Hierarchical Reuse and Dynamic Partitioning, Xueling Wang, Yuzhou Chen, Zhican Wang, Pan Zhao, Renda Jian, Yitian Chen, Chen Zhang, Yang Hu and Guanghui He, in Proceedings of the 63rd ACM/IEEE Design Automation Conference, 2026.

💻 Projects

A LoongArch-based FPGA System for Handwritten Digit Recognition (Mar. 2024 – Jun. 2024)

National Undergraduate IC Innovation and Entrepreneurship Competition — Loongson Track

• Built a system-on-chip prototype on a domestic FPGA using a LoongArch processor IP for real-time handwritten digit recognition.
• Responsible for the design and verification of the matrix multiplication accelerator IP.

A Pipelined CNN Chip (Mar. 2024 – May 2024)

Digital Integrated Circuit Design Course Project

• Designed and implemented a pipelined architecture for a specified CNN workload.
• Performed logic synthesis and physical implementation using Synopsys DC and ICC, with an evaluated throughput of 422K input feature maps per second.

A Five-stage RISC-V Processor (Jun. 2024)

Computer Architecture Course Project

• Implemented a five-stage pipelined processor in Verilog supporting the RV32I instruction set.
• Optimized the design to handle pipeline hazards.

🎖 Honors and Awards

• 2026.12 National Scholarship for Master’s Students (硕士研究生国家奖学金) from Shanghai Jiao Tong University.
• 2024.12 Jiang Scholarship (蒋氏奖学金) from Shanghai Jiao Tong University.
• 2022–2024 Undergraduate Outstanding Student Scholarship, Class B (本科生B等优秀奖学金) from Shanghai Jiao Tong University.
• 2023.12 National Encouragement Scholarship (国家励志奖学金) from Shanghai Jiao Tong University.
• 2022.10 Merit Student (三好学生) from Shanghai Jiao Tong University.

📖 Educations

SHANGHAI JIAO TONG UNIVERSITY Degree: Bachelor Period: 2021 – 2025 Major: Microelectronics Science and Engineering GPA: 3.99/4.30 (ranked 4th out of 76)

SHANGHAI JIAO TONG UNIVERSITY Degree: Master (in progress) Period: 2025 – 2028.03 (expected) Major: Integrated Circuit Science and Engineering GPA: 3.9/4.0